AT3 | AT91RM9200 microcontroller implementation |
This course covers AT91RM9200 ARM-based MCU family
Objectives
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- This course provides an overview of the ARM920T core. Our course reference R1 - ARM7/9 implementation course details the operation of this core.
- The following courses could be of interest:
- USB Full Speed High Speed and USB On-The-Go, reference IP2 - USB 2.0 course
- Ethernet and switching, reference N1 - Ethernet and switching course
- CAN bus, reference IA1 - CAN bus course
- Theoretical course
- PDF course material (in English) supplemented by a printed version.
- The trainer answers trainees' questions during the training and provide technical and pedagogical assistance.
- At the start of each session the trainer will interact with the trainees to ensure the course fits their expectations and correct if needed
- Any embedded systems engineer or technician with the above prerequisites.
- The prerequisites indicated above are assessed before the training by the technical supervision of the traineein his company, or by the trainee himself in the exceptional case of an individual trainee.
- Trainee progress is assessed by quizzes offered at the end of various sections to verify that the trainees have assimilated the points presented
- At the end of the training, each trainee receives a certificate attesting that they have successfully completed the course.
- In the event of a problem, discovered during the course, due to a lack of prerequisites by the trainee a different or additional training is offered to them, generally to reinforce their prerequisites,in agreement with their company manager if applicable.
Course Outline
- ARM core based architecture, AMBA buses
- The main three blocks : platform, core and input / output peripherals
- Presentation of the core, architecture and programming model
- Operating modes : user, system, super, IRQ, FIQ, undef and abort
- ARM vs Thumb instruction sets, interworking
- Access to memory-mapped locations, addressing modes
- Stack management
- C-to-Assembly interface
- Exception mechanism, handler table
- MMU, format of page descriptor tables
- Cache operation
- Debug facilities
- Power supplies, internal regulator
- Power-on sequence
- Clock generator, on-chip oscillator, PLL
- Boot program
- Memory controller
- Internal high-speed flash
- External Bus Interface
- Power management controller
- Advanced interrupt controller
- Parallel input / output controller
- Peripheral DMA controller
- Periodic Interval Timer
- Windowed Watchdog
- Real-time timer
- 3-channel timer / counter
- 2-wire interface
- I2C protocol basics
- Transmit and receive sequences
- SPI
- Master / slave operation
- External chip-select
- Transfer sequence
- USART
- Individual baud rate generators
- IrDA modulation / demodulation
- RS485 support
- Flow control
- Synchronous Serial Controller
- I2S analog interface support
- Time Division Multiplexed support
- High speed continuous data stream capabilities
- Ethernet MAC
- Full duplex vs half duplex operation
- Accessing PHY registers, auto-negotiation
- Receive and Transmit buffer management, buffer descriptors
- Incoming frame filtering
- USB device
- Full speed operation
- Endpoint configuration
- USB host
- Overview of the OHCI specification
- Understanding how USB packets are prepared and scheduled for transmission, transfer descriptor
- Multimedia Card Interface (on demand)
- MMC and SD card basics
- Command / response protocol
- Read sequence
- Write sequence
- Related interrupts