OVERVIEW
- 5-bus architecture, organization of a board based on MV64560
- Frequency domains, fast path between CPU and SRAM / SDRAM
- Internal crossbar
- Master de-mux programming, address decode windows
- Slave mux programming, pizza arbiters operation
- Compatibility with MV64460
CPU INTERFACE
- CPU address space decoding
- Protection windows
- Arbitration, multi-processor operation
- CPU slave operation
- CPU master operation (60X mode)
- Cache coherency
- Deadlock avoidance
DDR1/2 INTERFACE
- Introduction to DDR SDRAM from Jedec specification
- Differences between DDR1 and DDR2
- DDR2 on-die terminations
- Initialization sequence
- DDR1/2 SDRAM controller
- Page management
- Transaction ordering
- Cache coherency
- ECC and read-modify-write transactions
- Low power modes
DEVICE CONTROLLER
- Functional description
- Address and data multiplexing
- Connecting 8/16 bit devices
- External acknowledgement
- Pack / unpack and burst support
- NAND flash support, boot from NAND flash
PCI INTERFACE
- PCI bus arbitration
- Master operation in PCI and PCI-X mode
- Target operation in PCI and PCI-X mode
- PCI-to-PCI configuration transactions
- Address decoding
PCI-EXPRESS x4 INTERFACE
- Integrated low power SERDES PHY
- x1, x4 link
- Operating as either Root Complex or Endpoint
- Link initialization
- Arbitration and ordering
- Messaging unit
GENERAL PURPOSE INPUT/ OUTPUT PINS
- GPIO port, functional description
- Interrupt request inputs
- Multi Purpose Pin multiplexing
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INTERRUPT CONTROLLERS AND TIMERS
- Timers / counters
- Interrupt controller functional description
- Priority mechanism
TWSI CONTROLLER AND RESET
- I2C protocol basics
- TWSI controller functional description
- Master write sequence, master read sequence
- Slave write sequence, slave read sequence
- Reset pins and configuration
- Serial ROM initialization
- Requirement for an external Central Resource CPLD
IDMA CHANNELS
- IDMA address decoding
- Target unit and attributes programming
- Normal mode vs chained mode
- Transfer descriptors, descriptor ownership
- DMA interrupts
XOR ENGINES
- State machine : Active, Inactive and Paused states
- XOR operation mode
- CRC32 operation mode
- DMA operation mode
- Memory Initialization operation mode
- ECC error cleanup operation mode
- XOR Engines interrupts
16550 COMPATIBLE UARTs
- FIFO mode
- Flow control
- Transmit sequence
- Receive sequence
USB2.0 PORTS
- Address decoding
- Integrated PHY
- USB host operation, EHCI specification support
- USB device operation, Endpoint configuration
GIGABIT ETHERNET CONTROLLERS
- Interface to the PHY
- SGMII support
- Dedicated DMA
- Transmit weighted round-robin arbitration
- Backpressure mode
- Transmit and receive sequences
- Management interface
- Synchronous FIFO interface
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