Cette formation est-elle disponible en ligne ?

Oui, cette formation est disponible en présentiel et en ligne (visioconférence Teams).

Quels sont les prérequis pour cette formation ?

Good knowledge of PCIe gen2 protocol, see our course reference cours IC4 - PCI Express 3.0 Good knowledge of VHDL. Experience with simulation tools such as Mentor Graphics ModelSim. Basic knowledge of Xilinx ISE software.

Formation Xilinx - Spartan-6 / Virtex-6 Integrated PCI Express Block

Objectives

An introduction to PCI Express protocol is done at the beginning to be able later to understand the operation of the back-end bus.
The course details the parameterizing of the PCI Express core.
User interfaces are deeply detailed.
Management of errors and interrupts is studied through examples.
Guidelines to design the user logic are provided.
The course targets hard PCI Express cores in the Virtex-6 and Spartan-6 FPGAs.

	Xilinx software (ISE) is used to synthesize and implement practical examples, Mentor Graphics ModelSim is used for simulation.
	A more detailed course description is available on request at formation@ac6-formation.com

Prerequisites

Good knowledge of PCIe gen2 protocol, see our course reference cours IC4 - PCI Express 3.0
Good knowledge of VHDL.
Experience with simulation tools such as Mentor Graphics ModelSim.
Basic knowledge of Xilinx ISE software.

Environnement du cours

Cours théorique

Support PDF (en anglais), imprimé en présentiel ; à distance via Teams.
Assistance du formateur tout au long de la formation.

Chaque session débute par un point avec les stagiaires.

Audience visée

Tout ingénieur ou technicien en systèmes embarqués possédant les prérequis ci-dessus.

Modalités d'évaluation

Les prérequis sont vérifiés avant l'entrée en formation, sur la base des prérequis publiés sur cette fiche.
Pendant la formation, les acquis sont évalués en continu : quiz de fin de séquence et observation directe du formateur.
À l'issue de la formation, chaque participant reçoit une attestation de fin de formation.

1st DAY

PCI express protocol overview

Introduction to PCI Express
Transactions types and categories
Address Space Map and Configuration Space
PCI type0 basics, PCI express capability structure

PCI express and xilinx core generator

Selecting link speed and width
Address decoding logic, BAR registers setting
TLP buffer sizing
Power management configuration
Optional capability structures

Simulating a pcie design

Identifying simulation points
Simulation Methods
Building TestBench

Connecting logic to the core – local link or AXI interface

Clocking and reset
Common Transaction Interface Signals
Cut-through vs Store & Forward operation
Migrating to the integrated block for PCI Express v2.x from v1.x
AXI interface signals description
Managing control flow information to optimize the user logic

2nd DAY

Designing a simple endpoint application

PIO example description
Endpoint application and PCI Express core connection
Local Link or AXI interface
Accessing configuration space from user logic

Compliance and debugging

Chipscope Pro Description
Compliance Testing
Tracking the transitions in the LTSSM (Virtex-6)
Dynamic reconfiguration (Virtex-6)

Errors and interrupts

PCIe Error management, related registers
Introduction to legacy interrupts, MSI and MSI-X
Collaborating with PCIe block to generate error messages
Triggering interrupts, MSI or MSI-X from user logic
Explaining the benefits of MSI / MSI-X with respect to legacy interrupts