SWITCH ARCHITECTURE
- Stack, TLP routing, possible port splitting
- Switch core
- DMA modules
RESET AND INITIALIZATION
- Switch fundamental reset sequence
- Boot configuration vector
- SWMODE[3:0] configuration pins
- Enumeration software
- Runtime reconfiguration
LINK AND PHY OPERATION
- Lane reversal
- Link width negotiation in case of bad lanes
- Dynamic link width reconfiguration
- Link speed negotiation
- Link retraining
- Crosslink
HARDWARE IMPLEMENTATION
- Clocking, global reference clock and port reference clock
- Port global clocked mode, port local clocked mode
- Support of spread spectrum clocking
PARTITIONABLE PCI EXPRESS SWITCH
- Associating ports to form a completely independent PCIe switch
- Port configuration, transparent bridge, Non-Transparent (NT) bridge, DMA endpoint
- Multi-function ports
- Port operating mode change
- Highlighting ports supporting DMA function and port supporting NT function
- NT interconnect
- NT mapping table, address translation
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